News Release

EVE Expands Hardware Verification Platform Family

Rolls Out ZeBu-UF4, Adds RTL Front End to ZeBu Compiler

SAN JOSE, Calif. –– June 5, 2006 – EVE today introduced two new products to the growing ZeBu family, a line of comprehensive and fast hardware assisted verification platforms that enables simultaneous hardware and embedded software verification.

ZeBu-UF4 (for ultra-fast) shortens time to tapeout, improves product quality, eliminates costly respins and accelerates software development ahead of silicon. A new register transfer level (RTL) front end (F/E) extends the ZeBu Compiler from a gate-level netlist to an RTL design description and includes field programmable gate array (FPGA) synthesis capabilities.

"ZeBu-UF4 completes the ultra-fast ZeBu family, and support for RTL makes it a formidable challenger to established emulation solutions," says Lauro Rizzatti, vice president of worldwide marketing and general manager of EVE-USA. "Our offerings outdistance existing products bogged down by slow speed and outrageously high costs that relegate them to hardware debugging applications and disqualify them for hardware/software integration and embedded software validation."

ZeBu-UF4 includes four Xilinx Virtex-4 LX200 FPGAs to accommodate designs of up to six million application specific integrate circuit (ASIC) logic gates, with memory capacity of four gigabits. Based on a PCI card with a mother-daughter scheme, it features an extensive Low Voltage Differential Swing (LVDS) interconnect array implemented on a printed circuit board (PCB) with a total of 68 layers.

Depending on the design structure, when performing in-circuit emulation (ICE) or executing synthesizable test benches (STB) ZeBu-UF4 can achieve a maximum performance of 20 to 40 megahertz (MHz). In co-emulation at the transaction level, it can reach 20 MHz. Through its reconfigurable testbench (RTB), it allows for interactive hardware debugging, including memory read and write, register read and write, continuous internal state capture, instantaneous snapshot at maximum speed and state save and restore.

ZeBu's RTL F/E maps an RTL design into an array of FPGAs, automatically handling all the required tasks including RTL parsing, synthesis, clustering, clocktree, bus and memory handling, and place and route. It supports parallel and incremental synthesis and place and route for fast re-compilation of design changes. It also enables RTL debugging by preserving RTL names in the design database.

The entire ZeBu line of hardware assisted verification platforms will be demonstrated during the 43rd Design Automation Conference (DAC) July 24-27 at the Moscone Center in San Francisco in Booth #924.

Pricing and Availability

ZeBu-UF4 is shipping now starting from $60,000; the RTL F/E is shipping now and is priced at $10,000.

For more information about EVE and ZeBu, contact Lauro Rizzatti, general manager of EVE USA. He can be reached at (408) 855-3201 or via email at lauro@eve-team.com.