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Session 1 (FPGA Prototyping) : Easy FPGA Prototyping with Xilinx Virtex-5: combine the fastest and largest FPGAs to date with full RTL visibility and discover what an amazing prototyping platform you can build. Session 2 (HW/SW Co-Verification) :HW/SW Co-Verification Methodology: learn how to verify hardware and software concurrently using multiple concurrent levels of abstraction, on a platform that delivers billions of cycles per simulation, enough to boot Operating Systems, debug device drivers and full applications. Session 3 (ESL) :ESL and Transaction-Level: learn how to mix a transaction-level testbench or ESL environment with emulation. Session 4 (ARM Emulation) :ARM Emulation: most SOCs include one or multiple ARM cores. What are the tricks to connecting your favorite software debugger to an emulator? Should you use a CCM model, RTL or Logic Tile? What about other key IP such as AMBA or AXI buses?
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