Processor Models
Most SOCs include one or more embedded processor cores. While Zebu is a generic platform for hardware debugging of any SOC, certain optimizations and customization are available to better serve software developers and to ease the mapping of the processor models in emulation.
Pre-Verified Models
Some embedded cores are available as Soft IP, so their RTL will be processed directly by the ZeBu compiler. Other cores are only available as hard macros, in which case EVE offers various solutions to integrate those cores into a complete emulation project.
For some cores, EVE also offers sample memory sub-systems so you can quickly build a software development platform, that you can later refine to include your entire SOC. In effect, those become equivalent to a fast Instruction Set Simulator (ISS), running an order of magnitude or more faster than a standard software ISS, and with perfect cycle accuracy, since the model is the actual processor RTL.
Integration With Software Development Toolchains
Debugging software on the real design is a key benefit of fast emulation. EVE has developed close partnerships with the embedded processor vendors to provide a closer integration between ZeBu and their software development toolchain. Virtualization of interfaces such as JTAG for instance enables transparent HW/SW Co-Verification.
SEE ALSO
- Solution: ARM, MIPS, Tensilica, ARC, Power and Texas Instruments based SOCs
- Solution: HW/SW Co-Verification