ZEMI-3: Behavioral SystemVerilog Compiler for Transactor BFMs
The key to transaction-based emulation is the BFM that converts high-level messages on the testbench side into signal-level activity on the design side. That BFM must be synthesized in hardware and emulated next to the DUT in order to achieve both high transaction performance and perfect cycle accuracy. Historically, writing that BFM was the main challenge of transaction-based emulation, by requiring engineers with expertise in both software and RTL design.
ZEMI-3 is a behavioral SystemVerilog compiler for transactor BFMs that makes it extremely easy to write cycle-accurate BFMs and exchange messages with a C++ or SystemVerilog testbench. It uses the familiar construct of the SystemVerilog language called "DPI", where each function call is indeed a transaction that is automatically off-loaded into the emulation hardware.
Features
- Automatic synthesis of behavioral SystemVerilog BFM
- Compiler automatically detects streaming for best performance
- Code for BFM is more compact and easier to maintain
- Overall 10X productivity improvement compared to SCEMI
SEE ALSO
- Solution: Transaction-Based Verification