ATPG Vector Simulation
ATPG vectors generated by Tetramax (Synopsys tm), Fastscan (Mentor tm) etc. tools are simulated with the gate level netlist to verify correctness. ATPG simulations can be run as gate level functional simulations.
ATPG simulations typically tend to be very long simulations. These simulations also stress the SW simulators because these are done using the gate level netlist.
They also have a lot of activity causing the SW simulator have very low CPS. For these reasons ATPG simulations consume a significant amount of compute resources and quite a few SW simulator licenses.
With the ZeBu-AX accelerator the ATPG simulations can be done significantly faster. Typical speed up that can be expected is in the 100x to 500x depending on the design size. The reason for this is that ZeBu-AX does not slow down with increased activity level in the design.
Since the ZeBu-AX compiler can easily handle udp and gate level constructs efficiently it is very easy to target a gate netlist using ZeBu-AX. The ZeBu-AX compiler is also extremely fast (upwards of 100M gate / hour) allowing multiple iterations of ATPG simulations if needed. Also since ZeBu-AX has very good debug capability it is very useful to debug ATPG vectors as well.
The waveforms generated from ZeBu-AX are complete (state and combinatorial nodes) and does not require the user to have to reconstruct any portion of the design. This eliminates the need for waveform creation on demand, which can be very slow especially in a ATPG environment where the activity level is high.
SEE ALSO
- Product: ZeBu-AX
- Solution: Simulation Acceleration